The semiconductor integrated circuit (IC) industry has experienced exponential growth. Technological advances in IC materials and design have produced generations of ICs where each generation has smaller and more complex circuits than the previous generation. In the course of IC evolution, functional density (i.e., the number of interconnected devices per chip area) has generally increased while geometry size (i.e., the smallest component (or line) that can be created using a fabrication process) has decreased. This scaling down process generally provides benefits by increasing production efficiency and lowering associated costs. Such scaling down has also increased the complexity of processing and manufacturing ICs and, for these advancements to be realized, similar developments in IC processing and manufacturing are needed.
For example, a field effect transistor (FET) typically includes source and drain (S/D) features disposed on opposing sides of a gate stack. The gate stack is surrounded by a gate spacer for protecting the gate stack as well as improving the gate stack's electrical performance. However, the gate spacer is frequently damaged in subsequent manufacturing processes, such as mid-end-of-line (MEOL) processes. For example, photolithography and etching processes are used for defining and etching holes for S/D and gate vias (or plugs). The holes are sometimes misaligned with the underlying targets due to photolithography overlay errors. Consequently, the etching processes remove not only the target material but also a part of the gate spacer. This leads to degradation of the gate stack's performance, shorting of the S/D vias with the gate stack, and other reliability issues and defects in the IC device.